Verification Engineer

=9 Position Details
Job Title: Verification Engineer
Location: San Jose, California (Onsite)
=9 Job Overview
The selected engineer will:

• Led verification efforts for complete FPGA designs in high-end router products.
• Interpret design specifications and collaborate closely with design engineers to define verification scenarios
• Developed test plans, constrained-random verification environments, and generated test cases, regressions, and coverage reports.
• Implemented coverage metrics for stimulus and corner-case scenarios.
• Built object-oriented testbench infrastructure, BFMs, and UVM test cases.

=9 Required Qualifications

• Bachelor's in Electrical Engineering required; Master's preferred
• 7+ years of ASIC/FPGA verification experience
• Strong SystemVerilog proficiency with solid OOP concepts
• Hands on experience with UVM, BFMs, and verification environment development
• Knowledge of PCIe, Ethernet, I2C, SPI, MDIO, and other relevant interfaces