RTL Lead

Posted by Shiftcode Analytics, Inc

San Jose, CA

Permanent

Virtual
Onsite: San Jose, CA (Local)
USC and GC
Principal RTL Lead High-Speed Ethernet ASIC (400G/800G)
Rate: DOE

JD:

We are hiring a Principal RTL Lead to drive the design and development of next-generation Ethernet subsystems for custom ASIC silicon , supporting 400G/800G+ data center infrastructure .

This is a highly technical, hands-on role focused on solving complex challenges in high-speed digital design, multi-lane data processing, and Ethernet protocol implementation .

=' Key Responsibilities

Define micro-architecture for high-bandwidth datapaths and control logic
Lead SystemVerilog RTL design for Ethernet subsystems
Implement IEEE 802.3 standards , including:
RS-FEC (Reed-Solomon)
Multi-Lane Distribution (MLD)
Auto-Negotiation / Link Training (AN/LT)
Solve complex design challenges:
Wide datapaths (1024-bit+)
Timing closure at high frequencies
Clock domain crossing (CDC) across asynchronous boundaries
Lead integration of SerDes IP and ensure PHY MAC interoperability
Drive best practices across:
Lint / CDC / RDC
Power optimization (UPF)
Design quality for first-pass silicon success

Required Experience

10+ years in ASIC RTL design (SystemVerilog)
Proven track record of multiple successful tape-outs (7nm / 5nm / 3nm preferred)
Deep expertise in high-speed Ethernet (100G / 400G / 800G)
Strong understanding of MAC / PCS / FEC layers
Experience across full ASIC front-end flow (architecture RTL verification bring-up)
Ability to lead subsystem design and mentor engineers